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LTC2182CUP

LTC2182CUP

IC ADC

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Shenzhen
105 pcs
Shanghai
5783 pcs
Hong Kong
577 pcs
United States
3746 pcs
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Specifications of LTC2182CUP

Part Number LTC2182CUP
Date Code 2335
Quantity Available 10211 pcs
Manufacturer Linear Technology/Analog Devices
Lead Time Ship within 24 hours
QTY 2000
Datasheet LTC2182.pdf
Minimum Quantity More than 50pcs
Distributor SingSun
RoHS Status Lead free / RoHS Compliant
Ship From Hong Kong
Shipment Way EMS/SF/DHL/TNT/UPS/FedEx
Country of Assembly TAIWAN
Country of Diffusion USA
Lot Number KN38388.15
MSL 1
Packaging -
Base Product Number LTC2182
Number of Bits 16
Sampling Rate (Per Second) 65M
Number of Inputs 2
Input Type Differential
Data Interface Parallel
Configuration S/H-ADC
Ratio - S/H:ADC 0.042361111111111
Number of A/D Converters 2
Architecture Pipelined
Reference Type External, Internal
Voltage - Supply, Analog 1.7 V ~ 1.9 V
Voltage - Supply, Digital 1.7 V ~ 1.9 V
Features Simultaneous Sampling
Operating Temperature 0°C ~ 70°C
Package / Case 64-WFQFN Exposed Pad
Supplier Device Package 64-QFN (9x9)

LTC2182CUP Features

  • Two-Channel Simultaneously Sampling ADC
  • 77dB SNR
  • 90dB SFDR
  • Low Power: 160mW/115mW/78mW Total 80mW/58mW/39mW per Channel
  • Single 1.8V Supply
  • CMOS, DDR CMOS, or DDR LVDS Outputs
  • Selectable Input Ranges: 1VP-P to 2VP-P
  • 550MHz Full Power Bandwidth S/H
  • Optional Data Output Randomizer
  • Optional Clock Duty Cycle Stabilizer
  • Shutdown and Nap Modes
  • Serial SPI Port for Configuration
  • 64-Pin (9mm × 9mm) QFN Package

LTC2182CUP Applications

  • Communications
  • Cellular Base Stations
  • Software Defined Radios
  • Portable Medical Imaging
  • Multi-Channel Data Acquisition
  • Nondestructive Testing

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LTC2182CUP Description

The LTC2182 are two-channel simultaneous sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 77dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance.

DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.3LSBRMS.

The digital outputs can be either full rate CMOS, Double Data Rate CMOS, or Double Data Rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

The ENC+ and ENC inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

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