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AD9767ASTZRL

AD9767ASTZRL

IC DAC 14BIT DUAL 125MSPS 48LQFP

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Shenzhen
7008 pcs
Shanghai
1483 pcs
Hong Kong
8820 pcs
United States
2163 pcs
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Specifications of AD9767ASTZRL

Part Number AD9767ASTZRL
Date Code 2407
Quantity Available 19474 pcs
Manufacturer Analog Devices Inc.
Lead Time Ship within 24 hours
QTY 3000
Datasheet AD9767.pdf
Minimum Quantity More than 50pcs
Distributor SingSun
RoHS Status Lead free / RoHS Compliant
Ship From Hong Kong
Shipment Way EMS/SF/DHL/TNT/UPS/FedEx
Country of Assembly CHINA
Country of Diffusion TAIWAN,CHINA
Lot Number LQ48707.51
MSL 1
Packaging Tape & Reel (TR)/Cut Tape (CT)/Reel
Base Product Number AD9767
Series TxDAC+
Number of Bits 14
Number of D/A Converters 2
Settling Time 35ns (Typ)
Output Type Current - Unbuffered
Differential Output Yes
Data Interface Parallel
Reference Type External, Internal
Voltage - Supply, Analog 3 V ~ 5.5 V
Voltage - Supply, Digital 2.7 V ~ 5.5 V
INL/DNL (LSB) ±1.5, ±1.0
Architecture Current Source
Operating Temperature -40°C ~ 85°C
Package / Case 48-LQFP
Supplier Device Package 48-LQFP (7x7)
Mounting Type Surface Mount

AD9767ASTZRL Features

  • 14-bit dual transmit digital-to-analog converters (DACs)
  • 125 MSPS update rate
  • Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc
  • Excellent gain and offset matching: 0.1%
  • Fully independent or single-resistor gain control
  • Dual-port or interleaved data
  • On-chip 1.2 V reference
  • 5 V or 3.3 V operation
  • Power dissipation: 380 mW @ 5 V
  • Power-down mode: 50 mW @ 5 V
  • 48-lead LQFP

AD9767ASTZRL Applications

  • Communications
  • Base stations
  • Digital synthesis
  • Quadrature modulation
  • 3D ultrasound

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AD9767ASTZRL Description

The AD9767 are dual-port, high speed, 2-channel, 14-bit CMOS DACs. Each part integrates two high quality TxDAC+® cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP. The AD9767 offer exceptional ac and dc performance while supporting update rates of up to 125 MSPS.

The AD9767 have been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs.

A mode control pin allows the AD9767 to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate.

The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature.

The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9767 can be simultaneously updated and can provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%.

The AD9767 are manufactured on an advanced, low cost CMOS process. They operate from a single supply of 3.3 V to 5 V and consume 380 mW of power.

AD9767ASTZRL Tags

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