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AD7548JPZ-REEL

AD7548JPZ-REEL

IC DAC 12BIT LC2MOS 20PLCC

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Shenzhen
1739 pcs
Shanghai
7555 pcs
Hong Kong
5544 pcs
United States
4468 pcs
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Specifications of AD7548JPZ-REEL

Part Number AD7548JPZ-REEL
Date Code 2338
Quantity Available 19306 pcs
Manufacturer Analog Devices Inc.
Lead Time Ship within 24 hours
QTY 2000
Datasheet AD7548.pdf
Minimum Quantity More than 50pcs
Distributor SingSun
RoHS Status Lead free / RoHS Compliant
Ship From Hong Kong
Shipment Way EMS/SF/DHL/TNT/UPS/FedEx
Country of Assembly THAILAND
Country of Diffusion USA
Lot Number QC25298.43
MSL 1
Packaging Tape & Reel (TR)
Base Product Number AD7548
Series -
Number of Bits 12
Number of D/A Converters 1
Settling Time 1.5μs (Typ)
Output Type Current - Unbuffered
Differential Output No
Data Interface Parallel
Reference Type External
Voltage - Supply, Analog 5V, 11.4 V ~ 15.75 V
Voltage - Supply, Digital 5V, 11.4 V ~ 15.75 V
INL/DNL (LSB) ±1 (Max), ±1 (Max)
Architecture R-2R
Operating Temperature 0°C ~ 70°C
Package / Case 20-LCC (J-Lead)
Supplier Device Package 20-PLCC (9x9)
Mounting Type Surface Mount

AD7548JPZ-REEL Features

  • All Grades 12-Bit Monotonic Over Full Temperature Ranges
  • Skinny DIP and Surface Mount Packages
  • 8-Bit Bus Compatible 12-Bit DAC
  • Low Gain Drift of 5 ppm/°C Maximum
  • Full 4 Quadrant Multiplication
  • Operation Specified at +5V, +12V or +15V Power Supply

AD7548JPZ-REEL Applications

  • 8-bit microprocessor based control systems
  • Programmable amplifiers
  • Function generation
  • Servo Control

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AD7548JPZ-REEL Description

The AD7548 is a 12-monolithic CMOS D/A converter for use with 8-bit bus microprocessors. Data is loaded in two bytes to input holding registers as shown in the block diagram opposite. The AD7548 can be configured to accept either left- or right-justified data, least significant byte or most significant byte first, using standard TTL compatible control inputs.

A separate load DAC control input allows the user the choice of updating the analog output coincident with loading new data to the DAC input register or at any time after the data loading event. This feature is especially important in multi-DAC systems where simultaneous update of all DACs is required.

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