IC DAC 16BIT 32CH SER 56-LFCSP
| Part Number | AD5372BCPZ-RL7 |
| Date Code | 2408 |
| Quantity Available | 11844 pcs |
| Manufacturer | Analog Devices Inc. |
| Lead Time | Ship within 24 hours |
| QTY | 1000 |
| Datasheet | AD5372.pdf |
| Minimum Quantity | More than 50pcs |
| Distributor | SingSun |
| RoHS Status | Lead free / RoHS Compliant |
| Ship From | Hong Kong |
| Shipment Way | EMS/SF/DHL/TNT/UPS/FedEx |
| Country of Assembly | PHILIPPINES |
| Country of Diffusion | IRELAND |
| Lot Number | MB75906.82 |
| MSL | 3 |
| Packaging | Tape & Reel (TR) |
| Base Product Number | AD5372 |
| Series | - |
| Number of Bits | 16 |
| Number of D/A Converters | 32 |
| Settling Time | 30μs |
| Output Type | Voltage - Buffered |
| Differential Output | No |
| Data Interface | SPI, DSP |
| Reference Type | External |
| Voltage - Supply, Analog | 9 V ~ 16.5 V, -4.5 V ~ 16.5 V |
| Voltage - Supply, Digital | 2.5 V ~ 5.5 V |
| INL/DNL (LSB) | ±4 (Max), ±1 (Max) |
| Architecture | String DAC |
| Operating Temperature | -40°C ~ 85°C |
| Package / Case | 56-VFQFN Exposed Pad, CSP |
| Supplier Device Package | 56-LFCSP-VQ (8x8) |
| Mounting Type | Surface Mount |
The AD5372 contain 32, 16-bit digital-to-analog converters (DACs) in a single 64-lead LQFP. The devices provide buffered voltage outputs with a nominal span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into four groups of eight DACs. Two offset DACs allow the output range of the groups to be altered. Group 0 can be adjusted by Offset DAC 0, and Group 1 to Group 3 can be adjusted by Offset DAC 1.
The AD5372 offer guaranteed operation over a wide supply range: VSS from −16.5 V to −4.5 V and VDD from 9 V to 16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.
The AD5372 have a high-speed serial interface, which is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on reception of new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the CLR pin.
