IC DAC 16BIT 40CH SERIAL 64LFCSP
| Part Number | AD5370BCPZ |
| Date Code | 2030 |
| Quantity Available | 32763 pcs |
| Manufacturer | Analog Devices Inc. |
| Lead Time | Ship within 24 hours |
| QTY | 1000 |
| Datasheet | AD5370.pdf |
| Minimum Quantity | More than 50pcs |
| Distributor | SingSun |
| RoHS Status | Lead free / RoHS Compliant |
| Ship From | Hong Kong |
| Shipment Way | EMS/SF/DHL/TNT/UPS/FedEx |
| Country of Assembly | CHINA |
| Country of Diffusion | KOREA |
| Lot Number | YB20886.14 |
| MSL | 1 |
| Packaging | Tray |
| Base Product Number | AD5370 |
| Series | - |
| Number of Bits | 16 |
| Number of D/A Converters | 40 |
| Settling Time | 30μs |
| Output Type | Voltage - Buffered |
| Differential Output | No |
| Data Interface | SPI, DSP |
| Reference Type | External |
| Voltage - Supply, Analog | 9 V ~ 16.5 V, -4.5 V ~ 16.5 V |
| Voltage - Supply, Digital | 2.5 V ~ 5.5 V |
| INL/DNL (LSB) | ±4 (Max), ±1 (Max) |
| Architecture | String DAC |
| Operating Temperature | -40°C ~ 85°C |
| Package / Case | 64-VFQFN Exposed Pad, CSP |
| Supplier Device Package | 64-LFCSP-VQ (9x9) |
| Mounting Type | Surface Mount |
The AD5370BCPZ contains forty 16-bit DACs in a single 64-lead LFCSP and a 64-lead LQFP. The device provides buffered voltage outputs with a span that is 4× the reference voltage. The gain and offset of each DAC channel can be independently trimmed to remove errors. For even greater flexibility, the device is divided into five groups of eight DACs. Three offset DAC channels allow the output range of blocks to be adjusted. Group 0 can be adjusted by Offset DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.
The AD5370 offers guaranteed operation over a wide supply range, with VSS from −16.5 V to −4.5 V and VDD from +9 V to +16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.
The AD5370 has a high speed serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on receipt of new data. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and an offset adjust register to allow removal of gain and offset errors.
Each DAC output is gained and buffered on chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the CLR pin.
