AD1895AYRS

The AD1895 is a 24-bit, high performance, single-chip, second generation asynchronous sample rate converter. Based upon Analog Devices'experience with its first asynchronous sample rate converter, the AD1890, the AD1895 offers improved performance and additional features. This improved performance includes a THD + N range of –115 dB to –122 dB depending on sample rate and input frequency, 128 dB (A-Weighted) dynamic range, 192 kHz sampling frequencies for both input and output sample rates, improved jitter rejection, and 1:8 upsampling and 7.75:1 downsampling ratios. Additional features include more serial formats, a bypass mode, and better interfacing to digital signal processors.
The AD1895 has a 3-wire interface for the serial input and output ports that supports left-justified, I²S, and right-justified (16-, 18-, 20-, 24-bit) modes. Additionally, the serial output port supports TDM Mode for daisy-chaining multiple AD1895s to a digital signal processor. The serial output data is dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is selected. The AD1895 sample rate converts the data from the serial input port to the sample rate of the serial output port. The sample rate at the serial input port can be asynchronous with respect to the output sample rate of the output serial port. The master clock to the AD1895, MCLK, can be asynchronous to both the serial input and output ports.
MCLK can either be generated off-chip or on-chip by the AD1895 master clock oscillator. Since MCLK can be asynchronous to the input or output serial ports, a crystal can be used to generate MCLK internally to reduce noise and EMI emissions on the board. When MCLK is synchronous to either the output or input serial port, the AD1895 can be configured in a master mode where MCLK is divided down and used to generate the left/right and bit clocks for the serial port that is synchronous to MCLK. The AD1895 supports master modes of 256 × f_S, 512 × f_S, and 768 × f_S for both input and output serial ports.
Conceptually, the AD1895 interpolates the serial input data by a rate of 2²⁰ and samples the interpolated data stream by the output sample rate. In practice, a 64-tap FIR filter with 2²⁰ polyphases, a FIFO, a digital servo loop that measures the time difference between input and output samples within 5 ps, and a digital circuit to track the sample rate ratio are used to perform the interpolation and output sampling. Refer to the Theory of Operation section. The digital servo loop and sample rate ratio circuit automatically track the input and output sample rates.